Does the transceiver reference clock need to be stable before ATX PLL calibration is performed on Stratix V GX/T and Arria V GZ devices? - Does the transceiver reference clock need to be stable before ATX PLL calibration is performed on Stratix V GX/T and Arria V GZ devices? Description Yes, the reference clock needs to be stable before ATX PLL calibration is performed on Stratix ® V GX/T and Arria ® V GZ devices. ATX PLL calibration is automatically performed after device configuration. Resolution If the transceiver reference clock is not stable during ATX PLL calibration, the calibration may fail. To manually restart ATX PLL calibration, you should use the Avalon Memory Mapped register space within the Transceiver Reconfiguration Controller. Please see the ATX PLL calibration section of the Transceiver PHY IP User Guide for more details on these registers. Related Articles How can I meet the Stratix V and Arria V GZ device ATX PLL calibration requirement that the transceiver reference clock must be present at the start of device configuration if I use the FPGA to program my clock synthesizer device? How can I recalibrate the Stratix V and Arria V GZ device ATX PLLs? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']