Why did the LPDDR5 Agilex™ 7 FPGA M-Series EMIF IP Design Example fail simulation? - Why did the LPDDR5 Agilex™ 7 FPGA M-Series EMIF IP Design Example fail simulation? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.2, you may see that the LPDDR5 example design has failed simulation in the Questa* FPGA Edition simulator. The same design is passing simulation in the VCS* simulator. Resolution There is no workaround for this problem. This problem is fixed starting with the Quartus® Prime Pro Edition Software version 23.4 Custom Fields values: ['novalue'] Errata 22018526196 True ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.2 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']