Why do I see hold time violations when using the 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP? - Why do I see hold time violations when using the 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP? Description Due to a problem with the 10GBASE-KY PHY Intel® Stratix® 10 FPGA IP you may see minor hold time violations in the 10GBASE-KR IP during compilation. Resolution A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 555464; True ['1G 10GbE and 10GBASE-KR PHY IP', 'Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']