Altera® FPGAs Timing Analysis: Hands-On Labs - This instructor-led class is taught in a virtual classroom over 1 half day of instruction. The class begins with a very short review of concepts, followed by a long period of time to work hands-on lab exercises. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training and pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. To attend a comprehensive presentation about timing analysis, sign up for the Altera® FPGAs Timing Analysis: Lecture class. Course Description This workshop is a follow on to the Altera® FPGAs Timing Analysis: Lecture class. There will be a brief review of the SDC constraints learned in the previous class before starting the labs. Course Objectives At course completion, you will be able to: Understand the Timing Analyzer timing analysis design flow Apply basic and intermediate timing constraints to an FPGA design Analyze an FPGA design for timing using the Timing Analyzer Write and manipulate SDC files for analysis and controlling the Quartus® Prime software compilation Skills Required Completion of the Quartus Prime Software: Foundation online or instructor-led course OR a working knowledge of the Quartus Prime software Understanding of basic hardware timing parameters and equations used in the timing verification OR completion of Introduction to Timing Analysis Completion of the Altera® FPGAs Timing Analysis – Lecture class If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_IDSW123. FPGA_IDSW123. <p>Altera FPGAs Timing Analysis: Hands-On Labs</p>