Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock? - Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock? Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only. Custom Fields values: ['novalue'] Troubleshooting QS-9816 novalue ['Interfaces Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 23.4 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs', 'Agilex™ 9 FPGA Direct RF-Series'] ['novalue'] ['novalue'] ['novalue']