Why are the Altera_PLL output clocks stuck low when simulating this megafunction in Cadence NCSim? - Why are the Altera_PLL output clocks stuck low when simulating this megafunction in Cadence NCSim? Description If you are using NCSim to simulate the Altera_PLL megafunction, some of the output clocks may be stuck low. Resolution There are two workarounds for this issue: 1. To instantiate Altera_PLL, check "Enable physical output parameters" in the megafunction, and set the parameters accordingly to get the clocks you want. 2. Enable the macro SIM_USE_ICD_PLL_RECONFIG_MODEL to use the physical simulation model as shown below for Cyclone® V devices. You will need to edit the commands below when targeting Arria® V or Stratix® V devices. ncvlog -DEFINE SIM_USE_ICD_PLL_RECONFIG_MODEL=TRUE "/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver This issue is fixed starting in the Quartus® II software version 13.1. Custom Fields values: ['novalue'] Troubleshooting 2205803068 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.1.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']