How can the fractional PLL bandwidth parameter be set to "high" in the PLL reconfiguration calculator for Stratix® V, Arria® V, or Cyclone® V devices? - How can the fractional PLL bandwidth parameter be set to "high" in the PLL reconfiguration calculator for Stratix® V, Arria® V, or Cyclone® V devices? Description In the phase-locked loop (PLL) reconfiguration calculator for Stratix® V, Arria® V, or Cyclone® V devices, the fractional PLL bandwidth setting is fixed to "low". It is not possible to modify the bandwidth setting in the calculator because the jitter specification in the datasheet only covers fractional PLLs with low bandwidth. Resolution If you need to reconfigure your fractional PLL bandwidth setting to "high", invoke the PLL Intel FPGA IP parameter editor, and enter the bandwidth settings along with the required counter settings. Generate a MIF file and look for the bit settings in this MIF file. Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']