50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design - MLE 50G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 50Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full… Missing Link Electronics (MLE) is a Silicon Valley-based technology company with offices in Germany. We have been enabling key innovators in the automotive, industrial, test and measurement markets… Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Cyclone® 10 GX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® III FPGA Stratix® IV GX FPGA Stratix® V GX FPGA Core Benefits: Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”). Increase network throughput and reduce transport latency. Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU is available (“Full Acceleration”). Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI. All MAC/Ethernet/IPv4/UDP/TCP processing is implemented in HDL code, synthesizable to modern FPGAs and ASIC. User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs. Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Defense Government Industrial Medical Test Transportation 50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design Key Features Highly modular TCP/UDP/IP stack implementation in synthesizable HDL Offering Brief No No No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Cyclone® 10 GX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® III FPGA Stratix® IV GX FPGA Stratix® V GX FPGA No No 25.1.1 Offering Brief Production a1JUi000006JLV7MAO What's Included Single-Project or Multi-Project Use for ASIC or FPGA Ordering Information npap-50g a1JUi000006JLV7MAO Production Design Services Intellectual Property (IP) a1MUi00000BO8sfMAD a1MUi00000BO8sfMAD Select 2026-04-21T12:58:34.000+0000 MLE 50G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 50Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full duplex data width, and pipelines all-RTL implementation for high throughput and ultra low Latency. Partner Solutions