Why does Stratix 10 HDMI design example Rx lock time is longer ? - Why does Stratix 10 HDMI design example Rx lock time is longer ? Description Due to a problem with the Stratix® 10 HDMI IP in Quartus® Prime Pro edition version 18.0, user may observe HDMI Rx takes longer time to lock for HDMI 2.0 resolution as compared to Arria® 10 HDMI IP Design Example. This is due to the change of the behavior in the rx_std_bitslipboundary_sel of Synchronous State Machine Word Alignment in Stratix 10 FPGA that incur additional delay causing HDMI IP Rx harder to achieve fast alignment. Resolution There is no workaround. This problem is fixed in Quartus® Prime Pro version 18.0 update 1. Custom Fields values: ['novalue'] Troubleshooting FB: 551763; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0.1 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']