I2S-TDM: I2S/TDM Multichannel Audio Transceiver - The I2S-TDM IP core is a configurable, full-duplex, multi-channel serial audio transceiver supporting both Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) interfaces. It can operate as… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 9 FPGA Direct RF-Series The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging multi-channel audio samples over a configurable number of serial lines (pins). The I2S-TDM offers a number of configuration options to satisfy a wide range of serial audio interface requirements. The operation mode (controller or target), sample width, sample rate, frame format, number of channels and their allocation to physical lines are all programmable at run time. At synthesis time, designers can choose the maximum number of audio channels and serial data lines the transceiver can support. The core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interface, or, optionally, an AXI4 Lite interface. The host system exchanges audio data with the core either via this CSR interface or via dedicated AXI4-Stream interfaces. The system interfaces operate with a clock that is independent from the audio master and serial bit clocks, and the core implements clean clock domain crossing boundaries. The I2S-TDM core is available in Verilog source code or as a targeted FPGA netlist. Its deliverables include a testbench, comprehensive documentation, sample simulation and synthesis scripts, and bare-metal device drivers. Video and Image Processing ASIC Proto Broadcast Consumer Defense Government Industrial Medical I2S-TDM: I2S/TDM Multichannel Audio Transceiver Key Features Supports I2S/TDM formats with left/right justification, full-duplex transmit/receive, and configurable audio channels and data lines Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 9 FPGA Direct RF-Series Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6fMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information I2S-TDM a1JUi0000049U6fMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:28.000+0000 The I2S-TDM IP core is a configurable, full-duplex, multi-channel serial audio transceiver supporting both Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) interfaces. It can operate as either controller (master) or target (slave), exchanging audio samples over programmable serial lines. Designers can configure parameters such as sample width (2–32 bits), sample rate, frame format, number of channels, and allocation per line at run time, while synthesis-time options define maximum supported channels and lines. Integration is simplified with APB or AXI4-Lite control interfaces and AXI4-Stream for audio data, with clean clock domain crossings. The core is delivered as Verilog RTL or FPGA netlist, with testbench, scripts, drivers, and documentation, and typically uses about 10K gates for an 8-channel configuration. Partner Solutions