Timing Violation for Arria 10 HDMI Design - Timing Violation for Arria 10 HDMI Design Description When you run the HDMI design for Arria 10 devices, the design may encounter timing violation within the dual-clock FIFO (DCFIFO) block. The DCFIFO block bypasses the HDMI video, audio, and auxiliary data from the receiver to the transmitter. The timing violation only occurs when you run the design in the Quartus Prime Pro Edition version 15.1. Resolution There is no workaround for this issue. This issue will be fixed in a future version of the HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']