Why do I encounter simulation error Agilex™ 7 FPGA DDR5 EMIF IP Design Example with VCS simulator: ACTIVATE command issued while vendor specified RAAMMT exceeded in Quartus® Prime Pro Edition Software versions 23.2? - Why do I encounter simulation error Agilex™ 7 FPGA DDR5 EMIF IP Design Example with VCS simulator: ACTIVATE command issued while vendor specified RAAMMT exceeded in Quartus® Prime Pro Edition Software versions 23.2? Description Simulation error seen due to the lack of refresh management support in the EMIF IP. This causes the memory model to issue an error, RAAMT violation. However, since this does not affect the functional correctness of DDR5 RTL simulation for 23.3, the error message will be hidden from the DDR5 memory model to suppress this problem. Resolution The issue has been fixed in Quartus® Prime Pro Edition Software versions 23.3 and onwards version releases. Custom Fields values: ['novalue'] Troubleshooting 14020283027 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 23.4 23.2 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']