WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is x - WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is x Description When simulating UniPHY-based memory controllers, you may experience the above warning. The warning is caused by two uninitialized register files that are inadvertently accessed during the startup of the Nios sequencer in the memory controller. Resolution To fix this warning, implement the following workaround: 1) Open the altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v file 2) For the two instances of altsyncram, add the following line: the_altsyncram.intended_device_family = "STRATIXIV" Change the intended_device_family to the used FPGA device family (STRATIXIII, STRATIXIV, etc.). The instance should look like the following: altsyncram the_altsyncram ( .address_a (wraddress), .address_b (rdaddress), .clock0 (clock), .data_a (data), .q_b (ram_q), .wren_a (wren) ); defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.intended_device_family = "STRATIXIV", the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32, the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT", the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO", the_altsyncram.rdcontrol_reg_b = "CLOCK0", the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncramthe_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5; This issue has been fixed in Intel® Quartus® Prime Software version 12.1.1 Custom Fields values: ['novalue'] Troubleshooting 2205790958 False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 12.1.1 11.0 ['Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']