SEU Mitigation in Altera® FPGA Devices: Hierarchy Tagging - 14 Minutes In the SEU Mitigation in Altera® FPGA Devices: Hierarchy Tagging training, you will learn how you can improve your sensitivity processing solution by supplementing this single event upset (SEU) mitigation technique with another Altera® Stratix® 10, Altera® Arria® 10, Altera® Cyclone® 10 GX & Altera® Quartus® Prime Pro feature called hierarchy tagging. The result can be significantly less FPGA down time when an error caused by SEU occurs. You will understand how hierarchy tagging works, how to enable it in your FPGA design & how to use it when designing an SEU recovery solution. Though the class focuses on the Altera® Stratix® 10, Altera® Arria® 10 and Altera® Cyclone 10 GX families, some techniques are supported on select older device families. Please see your device user guide. Course Objectives At course completion, you will be able to: Define hierarchy tagging and how it can improve a single event upset (SEU) mitigation solution Enable hierarchy tagging and assign sensitivity IDs in the Altera® Quartus® Prime Pro software Implement control logic that uses hierarchy tags to filter responses to SEU Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus® Prime Pro design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OSEUHIER. FPGA_OSEUHIER. <p>SEU Mitigation in Altera FPGA Devices: Hierarchy Tagging</p>