Why is Questa slower than Modelsim? - Why is Questa slower than Modelsim? I was used to simulate with Intel-Modelsim SE 10.7c. I might have a new project using an Intel FPGA therefore I wanted to give Intel-Questa SE a try and I was surprised to see it's twice slower than Intel-Modelsim 10.7c version for the same design. Why? Is it normal? Modelsim runs under 32b and the new Questa is exclusively 64b, that's the only reason I could find. Replies: Re: Why is Questa slower than Modelsim? Hi @YEan , Interesting... this was my first hands-on with intel's tools. I now Questa delivered with Quartus pro 22.1 to avoid any compatibility issues. Regards, Replies: Re: Why is Questa slower than Modelsim? I have tried to run a small project in both of these simulators and I think the speed was same for me. Replies: Re: Why is Questa slower than Modelsim? Intel-Questa SE 21.1should be faster than Intel-Modelsim SE 20.1, I'm not sure why it is slow. I might need some time to look into it. Replies: Re: Why is Questa slower than Modelsim? Sorry, it's completely independent, Quartus plays no role here. Intel-Modelsim SE 20.1 vs Intel-Questa SE 21.1 , both provided by Intel with free license. I run my design with a tcl script, IIRC generated by a previous version of Quartus (com, elab ...) but that doesn't really matter. I'm talking about the speed of two simulators for an exact same design and tcl script. Intel has replaced Modelsim SE with Questa SE that is much slower. Replies: Re: Why is Questa slower than Modelsim? May I know which version of Quartus you are using ? Replies: Re: Why is Questa slower than Modelsim? @YEan I don't have any problem with my design. I'm comparing two free versions, Intel-Modelsim SE 20.1 and Intel-Questa SE 21.1 . I'd expect the same performance or even better for Questa for an exact same design. Especially when actually the factor is 2. Nevertheless, my benchmarking design has already `-voptargs="+acc"`. Am I wrong? Replies: Re: Why is Questa slower than Modelsim? Can you try to use compiler optimizations and only expose the modules/components you want to look at in the simulation with the +acc switch.