Default Termination of Stratix 10 Single Ended IO - Default Termination of Stratix 10 Single Ended IO Hi, What will be the default Termination resistance of Stratix 10 FPGA GPIO when configured as i) Input ii) output? With Regards, HPB Replies: Re: Default Termination of Stratix 10 Single Ended IO Hi, Thank you for your reply. With regards, HPB Replies: Re: Default Termination of Stratix 10 Single Ended IO Hello , For the single ended IO standard such as LVCMOS or LVTTL internal termination resistor is not supported . From the table 9 in the below link shows it supported channel. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-gpio.pdf Also refer Table 4 and Table 5 supported programmable feature and default state for each IO stand's. Thank you , Regards, Sree