Why does the Intel® Quartus® Prime Software device pin-out show a different number of pins compared to the Intel® Cyclone® 10 LP Device Overview document? - Why does the Intel® Quartus® Prime Software device pin-out show a different number of pins compared to the Intel® Cyclone® 10 LP Device Overview document? Description When targeting Intel® Cyclone® 10 LP devices in the Intel® Quartus® Prime Software, you will notice that there is 1 pin difference in the total pin count if compared to the Intel® Cyclone® 10 LP Maximum Resources in the Intel® Cyclone® 10 LP Device Overview document. For example, the Intel® Quartus® Prime Software lists 151 I/O pins for 10CL025YU256I7G, but in other documents it is listed as 150 I/O pins. Resolution This difference is because in the Intel® Quartus® Prime Software, the DCLK is counted as an I/O, since it can be used in user mode but in the respective device pin table, DCLK is not counted as an I/O. Thus, you will find 1 pin difference between what is stated in the Intel Cyclone 10 LP Device Overview document and the Intel Quartus Prime Software. Custom Fields values: ['novalue'] Troubleshooting 1408204953 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 19.4 ['Cyclone® 10 LP FPGA'] ['novalue'] ['novalue'] ['novalue']