Why do I get sdc warning messages regarding altpcie_ltssm_fifo.sdc and altpcie_link_inspector.sdc, when compiling designs which instantiate the Intel® Stratix® 10 Hard IP for PCI Express* IP? - Why do I get sdc warning messages regarding altpcie_ltssm_fifo.sdc and altpcie_link_inspector.sdc, when compiling designs which instantiate the Intel® Stratix® 10 Hard IP for PCI Express* IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.0 and 18.0.1, you may see some sdc warning messages when compiling a design which instantiates the Intel® Stratix® 10 Hard IP for PCI Express* with the Link Inspector enabled. These warnings are related to the Intel® Stratix® 10 Hard IP for PCI Express* IP core sdc files: altpcie_ltssm_fifo.sdc and altpcie_link_inspector.sdc . Here are some of the compilation warning messages: Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(66):<your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(67):<your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(79): <your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(80): <your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_link_inspector.sdc(15): *reconfig_clk_in_clk* could not be matched with a port Warning(332174): Ignored filter at altpcie_link_inspector.sdc(17): reconfig_clock_100Mhz could not be matched with a clock Warning(332174): Ignored filter at altpcie_link_inspector.sdc(17): *|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|xcvr_hip_native|ch0* could not be matched with a clock Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(66): <your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(67): <your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(79): <your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_ltssm_fifo.sdc(80): <your PCIe instantiation path>|hip|altera_pcie_s10_hip_ast_pipen1b_inst|g_pcie_link_insp.g_link_insp.altpcie_link_insp|ltssm_inst|ltssm_fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper Warning(332174): Ignored filter at altpcie_link_inspector.sdc(15): *reconfig_clk_in_clk* could not be matched with a port Warning(332174): Ignored filter at altpcie_link_inspector.sdc(17): reconfig_clock_100Mhz could not be matched with a clock Warning(332174): Ignored filter at altpcie_link_inspector.sdc(17): *|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|xcvr_hip_native|ch0* could not be matched with a clock Resolution To work around this problem, upgrade your design to Intel® Quartus® Prime Pro Edition software version 18.1. If you cannot upgrade your design, then replace the following files with the files provided in the link below. <your pcie instantiation path>/altera_pcie_s10_hip_avmm_bridge_180/synth/altera_pcie_s10_link_inspector/altpcie_ltssm_fifo.sdc <your pcie instantiation path>/altera_pcie_s10_hip_avmm_bridge_180/synth/altera_pcie_s10_link_inspector/altpcie_link_inspector.sdc altpcie_ltssm_fifo.sdc < link to updated file > altpcie_link_inspector.sdc < link to updated file > Custom Fields values: ['novalue'] Troubleshooting FB: 605972.Ã False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']