Why does tx_ready stuck low when using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP? - Why does tx_ready stuck low when using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP? Description When using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP with Fiber Channel RSFEC enabled, you may see tx_ready stuck low after triggering tx_reset . Resolution Although alignment marker is not needed when using RSFEC with Fiber Channel mode. You must still give tx_am_gen_2x_ack by counting tx_clkout cycles to complete the SRC handshake. Then tx_ready will go high after the handshake is complete. This note will be updated in a further release of the F-tile Architecture and PMA and FEC Direct PHY IP User Guide. Custom Fields values: ['novalue'] Troubleshooting 15012151975 False ['L-Tile H-Tile Transceiver Native PHY Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue No plan to fix ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']