The internal clock crossing bridge FIFO depth in the Quartus II software can cause setup timing violations - The internal clock crossing bridge FIFO depth in the Quartus II software can cause setup timing violations Description The Quartus II software does not infer embedded memories for an internal clock crossing bridge FIFO buffer if its depth is too small, which can lead to setup timing violations. Resolution Use an instance assignment to force inference of embedded memories for the FIFO buffer. For example, use set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to <design FIFO name>. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']