Why do I see errors from my simulation tool when compiling VHDL output netlists generated with the Maintain hierarchy option turned on? - Why do I see errors from my simulation tool when compiling VHDL output netlists generated with the Maintain hierarchy option turned on? Description Due to a problem in the Quartus® II software versions 10.1 and later, VHDL output netlists may contain errors if the netlist is generated with the Maintain hierarchy option in the More EDA Netlist Writer Settings . Due to missing signals within the netlist, typical errors you may see include: Unknown identifiers Illegal target for signal assignment Resolution To work around this issue, turn off the Maintain hierarchy option by following these steps: On the Quartus II Assignments menu, click Settings From the Category list, expand EDA Tool Settings and click Simulation Click More EDA Netlist Writer Settings Select the value Off for the Maintain hierarchy option This problem is fixed beginning with the Quartus II software version 12.0. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']