Why are my AXI-Lite register accesses to the PTP packet parser of the Ethernet Subsystem IP failing in 10G Asynchronous Clocking Mode? - Why are my AXI-Lite register accesses to the PTP packet parser of the Ethernet Subsystem IP failing in 10G Asynchronous Clocking Mode? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, AXI-lite register accesses to the PTP packet parser of the Ethernet Subsystem IP will fail in 10G Asynchronous Clocking Mode if the AXI-ST data path clock is slower than the AXI-Lite clock. Resolution To work around this problem, ensure that the AXI-Lite clock is slower than the AXI-ST data path clock. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 16020064328, 16019893838 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.1 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']