Why does the R-Tile IP for Compute Express Link* (CXL*) Type3 Design Example report a UVM_FATAL message when running simulation? - Why does the R-Tile IP for Compute Express Link* (CXL*) Type3 Design Example report a UVM_FATAL message when running simulation? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, you might observe the following error message when simulating the R-Tile IP for Compute Express Link* (CXL*) Type3 Design Example: UVM_FATAL /cxltyp3ddr_tb_23p1_acs/tb/verif/tb_top/cxl_tb_top.sv(255) @ 1000000.000ns: reporter [cxl_tb_top_initialize] Gen5 linkup failed. Timeout!!!! Resolution To work around this problem, update to a newer version of Avery BFM and install a patch for the Intel® Quartus® Prime Pro Edition Software version 23.1. Update Avery BFM version to apciexactor-2.5b.cxl; Download and install patch 0.08 from the files below. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 15013709705 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']