Ultra-high-throughput WiFi LDPC Decoder - XCEL ASICs’ Ultra-High-Throughput Wi-Fi LDPC Decoder IP is an IEEE 802.11n/ac/ax/be–compliant (Wi-Fi 4/5/6/7) forward error correction (FEC) solution optimized for current and next-generation Wi-Fi… XCEL ASICs is a deep-tech startup specializing in optimized silicon IP cores and design services. We design, simulate, implement, and verify high-performance digital systems targeting ASIC and FPGA… Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA This optimized silicon IP core is designed for IEEE 802.11 n/ac/ax/be (WiFi 4/5/6/7) compliant low-density parity-check (LDPC) decoding, addressing the growing demand for ultra-high-throughput solutions in WiFi transceiver chips with a minimal area footprint. The IP core can meet the stringent 30 Gbps throughput requirements of the latest WiFi 7 (IEEE 802.11be) standard. A cross-layer optimization of algorithm, architecture, and circuit has resulted in the best-reported power, performance, and area results for a WiFi-compliant LDPC decoder. Key features of the IP are: 1. Fully compliant with IEEE 802.11n/ac/ax/be (WiFi 4/5/6/7), 2. Achieves the best-reported power, performance, and area results, 3. Implements layered LDPC decoding for faster convergence, 4. Supports all WiFi code rates; 1/2, 2/3, 3/4, 5/6, 5. Supports all WiFi frame lengths: 648, 1296, 1944, 6. Has configurable max-iterations input. Error Correction ASIC Proto Wireless Ultra-high-throughput WiFi LDPC Decoder Key Features Fully compliant with IEEE 802.11n/ac/ax/be (WiFi 4/5/6/7). Offering Brief Yes No No Yes C/C++ Encrypted Verilog Verilog Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes 24.1.0 Offering Brief Production a1JUi000007dgjJMAQ What's Included Synthesizable Verilog or SystemVerilog RTL code Ordering Information dec-ldpc-wifi a1JUi000007dgjJMAQ Production Intellectual Property (IP) a1MUi00000BO8tmMAD a1MUi00000BO8tmMAD Select 2026-03-10T23:53:49.000+0000 XCEL ASICs’ Ultra-High-Throughput Wi-Fi LDPC Decoder IP is an IEEE 802.11n/ac/ax/be–compliant (Wi-Fi 4/5/6/7) forward error correction (FEC) solution optimized for current and next-generation Wi-Fi transceivers and SoC designs. In addition to supporting earlier Wi-Fi generations, the IP enables Wi-Fi 7 (IEEE 802.11be) data rates exceeding 30 Gbps while delivering exceptional throughput-per-area efficiency, enabling very high decoding performance within a minimal silicon footprint. This combination of scalable throughput and area efficiency makes the IP particularly well suited for cost- and power-constrained, high-performance Wi-Fi transceiver chip implementations. Partner Solutions