Why is there no response in AXI read data channel in Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP simulation? - Why is there no response in AXI read data channel in Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP simulation? Description When the signals in HBM2 AXI interface are set to unknown status before and after the read command in HBM2 simulation, you might see that there is no response in HBM2 AXI read data channel. Resolution Because there is no unkown status in actual hardware behavior, the signals in AXI interface will be captured as either 0 or 1, so the unknown status in simulation are not expected. To work around this, you can set the signlas in HBM2 AXI interface in simulation to random values instead of setting them to unknown status. Custom Fields values: ['novalue'] Troubleshooting 15010940784 False ['High Bandwidth Memory (HBM2) Interface IP'] ['FPGA Dev Tools Quartus® Prime Software'] No plan to fix 20.3 ['Stratix® 10 MX FPGA'] ['novalue'] ['novalue'] ['novalue']