Why are the inputs and/or outputs from my Agilex™ 7 FPGA device inverted? - Why are the inputs and/or outputs from my Agilex™ 7 FPGA device inverted? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and later, signals from the banks listed below may be inverted. This only affects IO Cells where any of the IO registers are enabled. Device GPIO Bank AGIB041, AGID041 3C and 3D AGFB006, AGFB008 3C and 3D AGFB012, AGFB014 3C and 3D AGFB019, AGFB023, AGFD019, AGFD023 AGIB019, AGIB023, AGID019, AGID023 3A and 3B AGFB022, AGFB027 AGIB022, AGIB027 3C and 3D Resolution To work around this problem, disable register packing for these GPIO banks. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016700000 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']