Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_logical_physical_mapping.cpp, Line: 563 - Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_logical_physical_mapping.cpp, Line: 563 Description Due to a problem in the Quartus® II software version 12.1 and later, you might see this internal error if you have multiple inputs of the rx_cdr_refclk port on the Stratix® V Native PHY connected to the same refclk pin. For example, this error might occur if ports rx_cdr_refclk(0) and rx_cdr_refclk(1) are both connected to pin refclk1 . Resolution To avoid this problem, connect each clock input of the CDR PLL to its own refclk pin. This problem is fixed starting with the Quartus® II software version 13.0. Custom Fields values: ['novalue'] Troubleshooting 1408014215 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']