When using the Intel® Arria® 10 PCIe Hard IP in CvP or Autonomous mode, can the PLLs or transceivers be recalibrated in user mode if the reference clock is not stable during power up. - When using the Intel® Arria® 10 PCIe Hard IP in CvP or Autonomous mode, can the PLLs or transceivers be recalibrated in user mode if the reference clock is not stable during power up. Description When using the Intel® Arria® 10 PCIe Hard IP in CvP or Autonomous mode, it is a requirement that the PCIe reference clock is either stable from power up or stable from the point it is enabled prior to the release of the nPERST#. The PCIe reference clock must not be unstable during the PCIe Hard IP phase-locked loop (PLL) or transceiver calibration phase. Resolution It is not possible to instigate a user mode re-calibration of the transceivers if this happens. Custom Fields values: ['novalue'] Troubleshooting 18012938604 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 20.1 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']