Can use double DDR3 IP in one FPGA? - Can use double DDR3 IP in one FPGA? Hi,everyone,now i want to use two ddr3-ip in one fpga,now i have some fpga that can select,but i don't know it whether or not can use,below is the fpga: 1.10AX027E4F29I3LG 2.1SX110HN2F43E2VG I want to use two DDR3-ip,only use ddr3-ip in fpga of the soc,if can,what should i do? Have some example？ thanks for your reply. Replies: Re: Can use double DDR3 IP in one FPGA? As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Replies: Re: Can use double DDR3 IP in one FPGA? Hello Sir, One DDR3 EMIF IP will maximize 3 IO Banks. If it's uses a smaller interface width, then it's requires less IO Bank. Both of the devices are able to support two EMIF IP. You can check in the EMIF Device Selector Tool to find the estimation of the IO Bank usage based on the number of EMIF IP. You may visit to EMIF IP Support Center to download the tool; https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html Some of the example projects that you can refer to is in Intel Development Kit. https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html Regards, Adzim