Internal Error: Sub-system: SIN, File: /quartus/h/sin_micro_tnodes_enum_translator_auto.cpp. Line: 5985 - Internal Error: Sub-system: SIN, File: /quartus/h/sin_micro_tnodes_enum_translator_auto.cpp. Line: 5985 Description In the Quartus® II software version 13.0sp1, you may see this internal error when running the PowerPlay Power Analyzer if a transceiver receiver channel uses either the LVDS or the Differential LVPECL I/O standard, targeting Cyclone® V, Arria® V, and Stratix® V devices. The power analyzer misidentifies transceiver channels as general-purpose I/O (GPIO) pins, but the GPIO pins do not have data on HSSI-specific termination settings. Resolution A patch is available to fix this for the Quartus® II software version 13.0sp1. Download the Windows patch 1.42 (.exe) Download the Linux patch 1.42 (.run) Download the readme file 1.42 (.txt) This patch allows the power analyzer to correctly identify transceiver channels and retrieve the appropriate data for its calculations. This problem is fixed in Intel® Quartus® 13.1. Custom Fields values: ['novalue'] Troubleshooting 1408030016 False ['Altera® FPGA Software Products'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']