Why do I see errors from my simulation tool about illegal names when compiling SystemVerilog output netlists? - Why do I see errors from my simulation tool about illegal names when compiling SystemVerilog output netlists? Description Due to a problem in the Quartus II software versions 11.0 and later, output netlists in SystemVerilog format may contain illegal names with an extra white spaces inserted. For example, a wire or net renamed by the Quartus II software may have an extra white space added: "\ renamed_net_3~0_combout” Resolution To work around this issue, follow the steps below: On the Quartus II Assignments menu, click Settings From the Category list, expand EDA Tool Settings and click Simulation Turn on the Map illegal HDL characters option Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']