TLS-02 - Quartus® Prime Software Timing Closure Masterclass - 2 Days - Enroll Now This advanced course equips experienced FPGA engineers with the skills and methodology to achieve reliable, repeatable timing closure on complex Altera® FPGA designs using Quartus® Prime Pro. The course assumes participants are already familiar with SDC syntax and focuses instead on the engineering disciplines that actually close timing: diagnosing failure root causes, restructuring logic and pipelines, applying placement and fitter controls, and managing the full clock domain crossing (CDC) design space. The course addresses the complete timing closure lifecycle: from reading failing timing reports and identifying structural bottlenecks, through architectural remedies (pipelining, retiming, register balancing), physical design controls (Logic Lock regions, placement constraints, fitter effort and seed sweeping), to scripted closure loops and production sign-off. A dedicated module on SoC and multi IP timing challenges prepares participants for the complexity of modern Platform Designer based subsystems. Note: This is an advanced course. Participants are expected to have working SDC constraint authoring experience. Engineers needing to build SDC skills from the ground up should first attend the FPGA Authority “ SDC Constraints and Analysis Masterclass. ” Course Content: 1. Course Overview — Timing Closure as a Discipline 2. The Quartus Prime Timing Engine — Fitter, Placement, and STA Flow 3. TNS, WNS, and Slack — Interpreting Summary Metrics and Prioritizing Work 4. Critical Path Anatomy — Logic Depth, Routing, and Skew Contributions 5. Timing Report Navigation — report_timing, Timing Closure Floorplan, and Path Inspector 6. Timing Closure Methodology — A Structured, Iterative Approach 7. Understanding Timing Failures — Fan Out, Logic Depth, and Long Route Paths 8. Pipeline Insertion Strategies — Breaking Critical Paths at the Right Stage 9. Retiming and Register Balancing — Quartus Synthesis Controls 10. Resource Sharing and Logic Duplication Trade offs 11. Synthesis Pragmas — keep, preserve, dont_merge, syn_encoding 12. Timing Driven Synthesis Settings — Effort, Speed Grade, and Seed Selection 13. CDC Fundamentals — Metastability, MTBF Theory, and Failure Modes 14. Two Flop Synchronizer Design — Principles, Constraints, and Technology Mapping 15. MTBF Calculation and Synchronizer Margin Analysis 16. CDC Analysis in Quartus — report_cdc, Violation Categories, and Coverage 17. Applying CDC Constraints — set_clock_groups, set_false_path, and Cut Paths 18. Pulse Synchronizers and Enable Synchronizers for Simple Control Signals 19. CDC Design Review Checklist — Common Pitfalls and Anti Patterns 20. Multi Bit CDC — Why Single Bit Synchronizers Are Insufficient 21. Four Phase Handshake Protocol — Design, Timing, and Throughput Analysis 22. Gray Code Counters for Asynchronous Pointer Synchronization 23. Asynchronous FIFO Architecture — Design, Pointer Management, and Verification 24. Bus Synchronizers — MUX Recirculation and Enable Synchronizer Patterns 25. Logic Lock Regions — Placement Constraints for Timing Critical and CDC Paths 26. Fitter Effort Settings, Seed Sweeping, and Placement Optimization Directives 27. Reset Synchronization — Asynchronous Assert, Synchronous De-assert 28. Reset Domain Crossing — Handling Multiple Reset Domains Safely 29. Clock Safe State Machine Design — Encoding and Transition Safety 30. SoC and Multi IP Timing Closure Challenges — IP Generated Constraints and Boundary Analysis 31. Scripted Timing Closure Loops — Automated Compile, Check, and Report Flows 32. Timing Closure and CDC Sign-Off Checklist — Production Release Criteria 33. Industry Best Practices and Lessons Learned Prerequisites: - Practical experience writing RTL in VHDL or Verilog / SystemVerilog - Working knowledge of FPGA architecture concepts (LUTs, flip flops, routing fabric, PLLs, clock networks) - Experience with the Quartus Prime IDE — compiling a design and reviewing compilation and timing reports - Solid understanding of SDC constraint syntax: create_clock, create_generated_clock, set_input_delay, set_output_delay, set_false_path, set_multicycle_path - Understanding of setup/hold timing, slack, TNS/WNS metrics, and timing path anatomy Recommended: - Completion of the FPGA Authority “SDC Constraints and Analysis Masterclass” or equivalent constraint authoring training - Experience with at least one Altera FPGA family (Cyclone® V, Arria 10, Agilex, or similar) - Familiarity with Tcl scripting basics (variables, loops, procedures) - Prior exposure to clock domain crossing concepts Tools Required: - Quartus® Prime Pro Edition - Altera Timing Analyzer - Platform Designer - ModelSim-Altera FPGA Edition - Mentor Questa CDC (Questa Formal) (Optional) - Python 3.x Course Code: TLS-02. FA_TIMING.