Why is the Arria® V GZ Hard IP for PCI Express "Enable HIP Status Bus" always enabled? - Why is the Arria® V GZ Hard IP for PCI Express "Enable HIP Status Bus" always enabled? Description The PCI Express® tcl file "altera_pcie_avgz_hip_avmm_hw.tcl " found in the Quartus® II install directory: \altera\<your_version>\ip\altera\altera_pcie\altera_pcie_avgz_hip_avmm\ is missing the enable_hip_status such that the features are always enabled. Resolution The following lines need to be added after the set enable_hip_status_ext section to ensure the Hard IP Status Bus can be enabled and disabled: set enable_hip_status [ get_parameter_value CG_ENABLE_HIP_STATUS ] if { == 1 } { add_pcie_hip_port_status } This problem has been fixed in Quartus® II Software Version 14.0. Custom Fields values: ['novalue'] Troubleshooting 259822 False ['Arria® V GZ Hard IP for PCI Express IP'] ['FPGA Dev Tools Quartus II Software'] 14.0 12.0 ['Arria® V GZ FPGA'] ['novalue'] ['novalue'] ['novalue']