Does the Agilex™ 7 FPGA M-series HPS EMIF support the External Memory Interface Debug Toolkit? - Does the Agilex™ 7 FPGA M-series HPS EMIF support the External Memory Interface Debug Toolkit? Description For Agilex™ 7 FPGA M-series (not for Agilex™ 7 FPGA F&I-series), the HPS EMIF controller does support the External Memory Interface Debug Toolkit. Using the following steps, create a design that instantiates the FPGA memory controller using the parameters for the HPS memory interface, and route it to the same I/O that the HPS EMIF uses. Related Information 11.5. Debugging with the External Memory Interface Debug Toolkit 1. Select the HPS EMIF IP within the Platform Designer project. 2. Click Dive Into Packaged Subsystem in the External Memory Interfaces for HPS IP window. 3. In the new window, single click on the EMIF IP inside the packaged IP window to view the Memory Device parameters on the right side, then click Generate Example Design . 4. Select the directory for the compile design: 5. The example design will be created. 6. Save and exit the Dive Into Packaged Subsystem window. Resolution The support will begin in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 22021390303 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 25.1.1 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']