Why are the SDC constraints for link clocks generated by the GTS JESD204B FPGA IP inaccurate? - Why are the SDC constraints for link clocks generated by the GTS JESD204B FPGA IP inaccurate? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may observe incorrect SDC constraints for link clocks generated by the GTS JESD204B FPGA IP. Resolution To work around this problem, update the value of period in the following constraints in ip/intel_jesd204b_gts_phy_<version>/synth/j204b_gts.sdc : create_clock -name "rxlink_clk" -period <period>ns [get_ports rxlink_clk] create_clock -name "txlink_clk" -period <period>ns [get_ports txlink_clk] where <period> is the calculated value of 1/(data rate/40). This problem has been fixed in the Quartus® Prime Pro Edition software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 15017126232 novalue ['Interfaces JESD204B (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']