Warning(18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "<SDC_FILE_PATH>/SDC_FILE.sdc")… - Warning(18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "<SDC_FILE_PATH>/SDC_FILE.sdc")… Description In the Quartus® Prime Pro Edition Software v21.4 and earlier, you may see this warning in Timing Analysis stage when compiling the Partial Reconfiguration (PR) Implementation Revision. Resolution You can ignore this warning if the <SDC_FILE>.sdc has been added to the PR Implementation Revision. If you didn’t, add the <SDC_FILE>.sdc to the project. Custom Fields values: ['novalue'] Troubleshooting 16014525019 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.2 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']