Why do I see timing violations in 1G/10G and 10GBASE-KR PHY FPGA IP? - Why do I see timing violations in 1G/10G and 10GBASE-KR PHY FPGA IP? Description Due to an issue in 1G/10G and 10GBASE-KR PHY FPGA IP, Quartus® Prime Standard Edition Design Software is unable to generate SDC file along with the IP files. Resolution As a workaround, download the file below. Check the following parameter values in the downloaded .sdc file and modify as per the design, if required: num_channels period_10g period_1g period_mgmt path_project Custom Fields values: ['novalue'] Troubleshooting 16028773344 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['Arria® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']