Why does the FIR II Intel® FPGA IP fail to generate in the Intel® Quartus® Prime Pro Edition Software version 22.1? - Why does the FIR II Intel® FPGA IP fail to generate in the Intel® Quartus® Prime Pro Edition Software version 22.1? Description The FIR II Intel® FPGA IP generates multiple Avalon streaming parameters when upgrading to the Intel® Quartus® Prime Pro Edition Software version 22.1. Error: ip_firII.fir_compiler_ii_0: There is an unknown error Error: ip_firII.fir_compiler_ii_0: Output Bit Width should be greater than 1 Error: ip_firII.fir_compiler_ii_0: Port ast_sink_data is not fully defined after elaboration Error: ip_firII.fir_compiler_ii_0: Port ast_source_data is not fully defined after elaboration Error: ip_firII.fir_compiler_ii_0.avalon_streaming_sink: data width (-1) must be a multiple of bitsPerSymbol (8) Error: ip_firII.fir_compiler_ii_0.avalon_streaming_sink: Signal ast_sink_data[-1] of type data must have width [1-8192] Error: ip_firII.fir_compiler_ii_0.avalon_streaming_source: Signal ast_source_data[-1] of type data must have width [1-8192] Error: ip_firII.fir_compiler_ii_0.avalon_streaming_source: "Data bits per symbol" (dataBitsPerSymbol) 0 is out of range: 1-131072 These errors only appear in Windows*. Resolution To work around this problem when using the Intel® Quartus® Prime Pro Edition Software version 22.1 of the FIR II Intel® FPGA IP, install patch 0.16 Custom Fields values: ['novalue'] Troubleshooting 18021657427 False ['FIR II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 22.1 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']