Chip planner - modern art? - Chip planner - modern art? Coming from Vivado, I don't understand how the Chip Planner can be useful to anybody. Here is an example: Why can't we see what block it is? its pins? Is it normal or there is an issue with the display? As a comparison with Vivado: In terms of UX, both apps are day and night. Regards, Replies: Re: Chip planner - modern art? To make sure what I'm seeing is actually what is expected. I couldn't believe it and wanted a confirmation. And also because I have no other choice than using Quartus... Replies: Re: Chip planner - modern art? Well you’ve clearly made your choice. So what’s the point of your post? Replies: Re: Chip planner - modern art? There aren't different tools, they are the exact same tool. The second screenshot is the Vivado's Chip planner equivalent. It exactly shows the actual resources used by the device and we can even see the routing resources. Surprising how obsolete Intel is, isn't it? We can even color the resources we want, with different colors: (source: https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2021_2/ug906-vivado-design-analysis.pdf ) I'll stop the comparison here, it's too shameful for Intel. From your answers, I assume the view is correct and is expected. Quartus is seriously miserable compared with the concurrent it tries to compete with. Replies: Re: Chip planner - modern art? Hi, Below are chip planner related links: https://www.intel.com/content/www/us/en/docs/programmable/683641/22-3/analyzing-and-optimizing-the-design-03170.html https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/optimize/ace/acv_view_acv_overview.htm https://www.google.com/search?q=intel+chip+planner&rlz=1C1GCEA_enMY1025MY1025&source=lnms&tbm=vid&sa=X&ved=2ahUKEwjkvp7O-Zj9AhVh1nMBHbhFAVoQ_AUoA3oECAEQBQ&biw=1920&bih=872&dpr=1#fpstate=ive&vld=cid:e918b180,vid:z82t12RCY_o Thanks, Best Regards, Sheng Replies: Re: Chip planner - modern art? These are two completely different tools. The Chip Planner is used to view device resources and how they are used by your design. You usually use the Chip Planner to analyze the results of place and route to help solve timing issues, but you can also use it to allocate resource usage for a part of the design. If you zoom out the image you posted, you'll see where these resources are physically located on the device. Your second screenshot is of a schematic editor or RTL viewer, a schematic representation of a design, not the actual resources used by the device. Quartus has a schematic editor and an RTL viewer that are used for a view like this.