Why do I measure high jitter on the “rx_clkout” pin of the F-Tile PMA/FEC Direct PHY FPGA IP or F-Tile PMA/FEC Direct Multirate FPGA IP variant? - Why do I measure high jitter on the “rx_clkout” pin of the F-Tile PMA/FEC Direct PHY FPGA IP or F-Tile PMA/FEC Direct Multirate FPGA IP variant? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, higher than expected jitter may be measured on the rx_clkout pin of the F-Tile PMA/FEC Direct PHY FPGA IP or the F-Tile PMA/FEC Direct Multirate FPGA IP cores when the CDR is set to lock-to-reference mode. Resolution There is no workaround for this problem. This problem has been fixed in version 24.2 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14021444125 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']