Ethernet 10G MAC IP: Failure During Elaboration Stage in NCSim/VHDL Simulation - Ethernet 10G MAC IP: Failure During Elaboration Stage in NCSim/VHDL Simulation Description When generating the v16.0 Ethernet 10G MAC IP Core with either of the following settings in VHDL, the auto-generated design fails during elaboration when compiled with the NCSIM simulator. 1. ENABLE_TIMESTAMPING = "1" or 2. ENABLE_1G10G_MAC = "1GBps/10Gbps" or "Multi-Speed 10 Mbps - 10 Gbps" Resolution Use the following command to generate the simulation script. make-ip-simscript --spd=<spd filename> --compile-to-work Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']