Simulation of Example Designs Can Fail or Produce Warnings for UniPHY External Memory Interfaces - Simulation of Example Designs Can Fail or Produce Warnings for UniPHY External Memory Interfaces Description The example design for simulation may fail to compile or trigger compiler warnings in either the VCS or NC Sim simulators, if the simulation scripts are generated from NativeLink. Resolution The following workarounds apply to this issue: For simulation in VCS, add the -debug_pp option to the .vcs file generated by� NativeLink. For simulation in NC Sim or any other simulator, remove the ; line from the <variation_name>_example_design/simulation/� <variation_name>_example_sim/submodules/status_checker.sv file. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 11.1 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']