Why is there a "reserved_mem_reserved_pins_for_dk_group" pin in RLDRAM II-UniPHY based controller in the Stratix V device? - Why is there a "reserved_mem_reserved_pins_for_dk_group" pin in RLDRAM II-UniPHY based controller in the Stratix V device? Description When you generate an RLDRAM II controller using Nios II-based sequencer, the MegaWizard™ will generate the top level IP module with the 2-bit wide signal reserved_mem_reserved_pins_for_dk_group . This signal serves no functional purpose but is needed to allow the dk pins to be assigned to a DQ group. In the Nios II-based sequencer instantiation, the dk pins must exist in a DQ group in order to access hardware required for calibration. You need to bring the reserved_mem_reserved_pins_for_dk_group signal up to the top level and connect it to a DQ pin in a x4 DQS group but there is no need to connect it to anything external to the FPGA as these pins serve no purpose. Resolution The reserved_mem_reserved_pins_for_dk_group signal is removed beginning with the Quartus® II software version 11.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1 11.0 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']