Why does Platform Designer hang when modifying a design with the Hard Processor System Intel® Stratix® 10 FPGA IP? - Why does Platform Designer hang when modifying a design with the Hard Processor System Intel® Stratix® 10 FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1, Platform Designer may hang when editing a system with the Hard Processor System Intel® Stratix® 10 FPGA IP because there is not enough Java heap space allocated by default. Resolution To work around this problem, increase the allocated java heap space as necessary by starting Platform Designer from the command line with the option “--jvm-max-heap-size=<size>m”. It is recommended to use 16384 for <size>, but this may need to be increased to 32768 for large systems. For example, “qsys-edit –jvm-max-heap-size=16384m my_project.qsys”. Custom Fields values: ['novalue'] Troubleshooting 2205689811 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.0 ['Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']