When using Active Parallel (AP) configuration mode can the DCLK frequency be set to a fixed frequency or can I use an external clock? - When using Active Parallel (AP) configuration mode can the DCLK frequency be set to a fixed frequency or can I use an external clock? Description No, the AP configuration mode uses the 40MHz internal oscillator for configuration and this cannot be changed nor can an external clock be used. When using the AP configuration mode the maximum DCLK frequency will be 40MHz. The typical DCLK frequency will be 33MHz with a minimum of 20MHz. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Cyclone® III FPGAs', 'Cyclone® IV E FPGA'] ['novalue'] ['novalue'] ['novalue']