Internal Error: Sub-system: U2B2_HVIO, File: /quartus/db/u2b2_hvio/u2b2_hvio_hviowr_translator_module.cpp - Internal Error: Sub-system: U2B2_HVIO, File: /quartus/db/u2b2_hvio/u2b2_hvio_hviowr_translator_module.cpp Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you might see this internal error during the Fitter stage for the Agilex™ 5 FPGA device. This problem occurs because the IO location for the design's IO port (and, more broadly, any IOs that support the 3.3-V LVCMOS IOSTD ) cannot simultaneously drive both the local H/V(horizontal and vertical wires) clock network and the global clock network. This is due to shared mux settings and is a limitation of the Agilex™ 5 FPGA device. Resolution To work around this problem, use either one of the following assignments in the Quartus® Prime settings file (.qsf): set_instance_assignment -name GLOBAL_SIGNAL ON -to <port name> set_instance_assignment -name GLOBAL_SIGNAL OFF -to <port name> This will resolve the split between global and local fanout, ensuring that the IO drives either entirely global or entirely local routing. The choice between ON or OFF depends on your use case and the signal's timing requirements. You are best positioned to figure out your design intent. Local routing might be preferable if the signal is more delay-sensitive (for example, due to potential data fanout), especially since it's otherwise a relatively low-fanout signal. Future versions of the Quartus® Prime Pro Edition Software are scheduled to generate an error message for this issue. Custom Fields values: ['novalue'] Troubleshooting 15017421550 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']