Why does the RapidIO II design example fail when simulating with the Aldec Riviera-PRO? - Why does the RapidIO II design example fail when simulating with the Aldec Riviera-PRO? Description The Intel® Stratix® 10 RapidIO* II design example in the Intel® Quartus® Prime Software version 17.1 and 17.1.1 might fail when simulating with the Aldec's Riviera-Pro 2017.02 when optimizations are turned on. Resolution If you are using the Riviera-Pro* 2017.02, turn off optimizations. This problem is fixed in the Intel® Quartus® Prime Software v18.0. Custom Fields values: ['novalue'] Troubleshooting FB: 495894; False ['RapidIO II (IDLE2 up to 6.25 Gbaud) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']