HPS Peripherals, Drivers & Device Tree Development - Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices. FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV GX FPGA Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices. Students write character device drivers, platform drivers, and DMA drivers, and learn to integrate custom FPGA IP blocks seamlessly into the Linux driver model. Coverage includes the Linux Device Model, DMA frameworks, and interrupt driven driver design. Participants gain hands-on experience configuring and extending the Device Tree to expose both HPS and FPGA fabric peripherals to the kernel. The course covers the complete driver development workflow: from kernel module compilation and Device Tree overlay authoring, through sysfs and debugfs instrumentation, to user space access via UIO and mmap. Each concept is reinforced with lab exercises targeting real Altera Cyclone V / Agilex SoC hardware. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless HPS Peripherals, Drivers & Device Tree Development Key Features Offering Brief No No No No Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV GX FPGA 2 Days No No English Offering Brief Production Windows,Linux a1JUi000009aGXJMA2 Working knowledge of C programming. Familiarity with Linux command line usage, shell scripting, and the GNU toolchain. Basic understanding of FPGA design concepts and HPS–FPGA bridge interfaces on Altera SoC devices. System Architects, Embedded Software Engineers, Hardware Engineers and Firmware Engineers What's Included PDF of slides, lab manual and lab files where applicable Ordering Information HPS Peripherals, Drivers & Device Tree Development a1JUi000009aGXJMA2 Production EDA Tools / IDE Education / Training a1MUi00000GbNhBMAV a1MUi00000GbNhBMAV Member 2026-07-16T20:47:02.000+0000 Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices. Partner Solutions