Why does CvP not work correctly when using the Avalon-MM PCIe Hard IP? - Why does CvP not work correctly when using the Avalon-MM PCIe Hard IP? Description Due to a known issue in Quartus® II software releases v12.0SP2 and earlier, Configuration via Protocol (CvP) will not work correctly if Avalon® MM mode is being used. Resolution To work around this issue in software version v12.0SP2, modify the auto-generated Qsys top level RTL file to ensure that the following parameters are set: .bypass_clk_switch_hwtcl ("false"), .cseb_cpl_status_during_cvp_hwtcl ("completer_abort"), .core_clk_sel_hwtcl ("core_clk_250"), .rx_ei_l0s_hwtcl (0), .enable_l0s_aspm_hwtcl ("false"), This issue is fixed in version 12.1sp1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1.1 11.0 ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']