Why is the Intel® HDMI* IP RX vid_lock signal deasserted when the video timing geometry is inconsistent? - Why is the Intel® HDMI* IP RX vid_lock signal deasserted when the video timing geometry is inconsistent? Description Due to a problem with the Intel® HDMI* IP, the signal RX vid_lock may not assert if video timing geometry is inconsistent. The HDMI RX IP checks for consistent HSYNC width, VSYNC width, Htotal, Hactive, Vtotal, and Vactive parameters across frames to qualify stable video and assert vid_lock . If these video parameters are inconsistent across frames vid_lock is deasserted and vid_data , vid_hsync , vid_vsync , and vid_de are invalid. Resolution This problem is fixed in version 17.1 of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 527473; True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 16.0 ['Arria® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']